Transient Error (TE) is when a combinatorial-gate (combo-gate) inside an electronic chip has a glitch on its output, for any reason, one of them is radiation related to cosmic ray and nuclear particles coming from space, mostly from the Sun. The glitch may cause the value of the output of the combo-gate to be flipped. The TE itself may not permanently damage the device, but this glitch may propagate through the combinatorial logic and get sampled by a flop or a group of flops. From there it can propagate and cause a glitch that disturbs an expected functionality of the device. These radiation induced TEs cause memory glitches by bit flipping the output of a single memory element. It will be noted, however, that TE can spontaneously occur in any circuit due to other reasons as well.
Soft error due to TE occurs when a glitch affects an electronic device operation in a substantive manner. Soft errors pose a major challenge for the design of Very-Large-Scale Integration (VLSI) circuits, and more particularly so in technologies smaller than about 90 nm. In other words, smaller technology in a dense microelectronics Integrated Circuit (IC) are more sensitive to this radiation, and this may spell higher probability of TEs to occur. Another significant factor affecting this probability is, the distance of the electronic device from the face of our plant, such as, avionics devices installed in high altitude aircrafts and space gears. The deeper in space the device operates, the more exposed to radiation interactions it become.
Since most semiconductor components are susceptible to radiation damage, a need for radiation-hardened components evolved. These radiation-hardened initially targeted the military and space industries were based on their commercial equivalents, with some design variations that reduce the susceptibility to radiation damage. Memory IC hardening may comprise, error correcting memory using additional parity or Error Correction Code (ECC) bits and a “scrubber” circuit to continuously sweep the memory cells. Redundant processing and logic elements may be used to replace a single memory element with three memory elements and separate “voting logic” between them to continuously determine its result, this way, if one of the three elements got hit by SEU, the voting will clear the error immediately. For protection from TEs, special kind of combinatorial gates are used that are bigger in silicon area and power consumption but are more resilient to TEs. However, as technologies get smaller these hardening techniques are charging a high price of power consumption; performance (e.g., speed, heat); silicon real estate; extensive development and testing; or the like.